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этимология

Что (кто) такое cache lines - определение

DYNAMICALLY MANAGED LOCAL MEMORY THAT MIRRORS MAIN MEMORY IN A MICROPROCESSOR TO REDUCE THE COST OF ACCESS

Level 1 cache; Level 2 cache; Cache line; CPU memory cache; Trace Caches; Trace caches; Cache block; Cache-line; L2 cache; L3 cache; L1 cache; CPU caches; CPU Cache; Data cache; Internal cache; Data Cache; First-level cache; L2-Cache; L1-Cache; Second-level cache; Secondary cache; Tag RAM; Direct mapped; Cpu cache; Instruction cache; L2 Cache; Cache flush; Motherboard cache; Discrete L2 cache; Level 3 cache; VIVT; VIPT; I cache; Processor cache; Internal and external cache; Multi-ported Cache; Smart Cache; CPU cache line; Copy-back; L4 cache; Micro-operation cache; Uop cache; Last level cache; Last Level Cache; Cache eviction; Exclusive CPU cache; Inclusive CPU cache; Exclusive cache; Inclusive cache; Multi-level cache; Multilevel cache; On-chip cache; Cache lines; Shared cache; Non-blocking cache; Branch target cache; Branch target instruction cache; SmartCache; Smart cache; L1d

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cache line

<storage> (Or cache block) The smallest unit of memory than can be transferred between the main memory and the cache. Rather than reading a single word or byte from main memory at a time, each cache entry is usually holds a certain number of words, known as a "cache line" or "cache block" and a whole line is read and cached at once. This takes advantage of the principle of locality of reference: if one location is read then nearby locations (particularly following locations) are likely to be read soon afterward. It can also take advantage of page-mode DRAM which allows faster access to consecutive locations. (1997-01-21)

secondary cache

<memory management> (Or "second level cache", "level two cache", "L2 cache") A larger, slower cache between the primary cache and main memory. Whereas the primary cache is often on the same integrated circuit as the {central processing unit} (CPU), a secondary cache is usually external. (1997-06-25)

level 1 cache

primary cache

L2 cache

secondary cache

cache block

cache line

L1 cache

primary cache

level 2 cache

secondary cache

CPU cache

A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations.

https://en.wikipedia.org/wiki/CPU_cache

Web cache

MECHANISM FOR THE TEMPORARY STORAGE (CACHING) OF WEB DOCUMENTS

Web caching; HTTP cache; Browser Cache; Browser Caching; Squirrel (DHT); Squirrel dht; Web caches; Proxy cache; Browser cache; Cache server; Internet cache; Http cache; HTTP caching; Webcache; Cache-Control; Web browser cache; Bypass your cache; Webcaching; List of server-side web caching software; Forward cache; Reverse cache

A Web cache (or HTTP cache) is a system for optimizing the World Wide Web. It is implemented both client-side and server-side.

https://en.wikipedia.org/wiki/Web_cache

Cache hierarchy

MEMORY HIERARCHY CONCEPT APPLIED TO CPU CACHES WITH MULTIPLE LEVELS

Cache Hierarchy

Cache hierarchy, or multi-level caches, refers to a memory architecture that uses a hierarchy of memory stores based on varying access speeds to cache data. Highly requested data is cached in high-speed access memory stores, allowing swifter access by central processing unit (CPU) cores.

https://en.wikipedia.org/wiki/Cache_hierarchy

Википедия

CPU cache

A CPU cache is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, located closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have a hierarchy of multiple cache levels (L1, L2, often L3, and rarely even L4), with different instruction-specific and data-specific caches at level 1. The cache memory is typically implemented with static random-access memory (SRAM), in modern CPUs by far the largest part of them by chip area, but SRAM is not always used for all levels (of I- or D-cache), or even any level, sometimes some latter or all levels are implemented with eDRAM.

Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) which most CPUs have.

https://en.wikipedia.org/wiki/CPU cache